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F16267 8-bit microcontroller with cir receiver release date: feb, 2009 version: 0.20p
finte k feature integration technology inc. v0.20p 1 F16267 F16267 datasheet revision history version date page revision history 0.10p dec, 2007 preliminary version 0.11p mar, 2008 7 10 13 add the lost description of pin 15 add current consumption description add all the register descriptions 0.12p apr, 2008 11 13-23 add internal 12mhz clock description revise register address 0.13p jul, 2008 13-15 revise register description 0.14p oct, 2008 20-24 register address: 7.38-7.53 0.15p oct, 2008 21-24 24 26 correct descriptions of alarm register 0x0087-0x008b remove the redundant register 0x8f ram data register ?index 00b090h~00efcfh (total 64 bytes) package dimensions ( 28 16 -ssop) 0.16p oct, 2008 25 correct the typo f16167r as F16267r 0.17p oct, 2008 6 revise pin configuration, swap pin 9 and 10 0.18p nov, 2008 19 add register 0x002f description 0.19p nov, 2008 11 13 15 23 24 add 6.5 watchdog timer function description add table 3 int0, int1 behavior add 6.6.3 power saving mode description remove register 0x0000~0x0007 description description of bit7 in register 0x008e: fp pf*pie = ?1? name of register 0x00fd: time_ middle low_byte 0.20p feb, 2009 17 18 19-20 20 register 0x0012, bit0: rx delay ? ready register 0x0015, 0x0017 default: 04h ? 80h register 0x0030, exchange the descriptions of bit 1 and 0 register 0x0032, 0x0033 typo revised
finte k feature integration technology inc. v0.20p 2 F16267 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support applia nces, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify fintek for any damages resulting from such improper use or sales.
finte k feature integration technology inc. v0.20p 3 F16267 table of contents 1 general description ............................................................................................................ ............................................ 6 2 feature ........................................................................................................................ ............................................................. 6 3 pin configuration .............................................................................................................. ................................................ 7 4 pin description................................................................................................................ ..................................................... 8 4.1. p ower p in ............................................................................................................................... ............................................ 8 4.2. gpio p in ............................................................................................................................... ............................................... 8 4.3. rtc p in ............................................................................................................................... ................................................. 8 4.4. i2c i nterface p in ............................................................................................................................... ................................ 9 4.5. ir p in ............................................................................................................................... .................................................... 9 5 electrical char acteristic...................................................................................................... ................................. 10 6 functional description ......................................................................................................... ...................................... 12 6.1 cir f unction ............................................................................................................................... ........................................ 12 6.2 rtc f unction ............................................................................................................................... ....................................... 12 6.3 i2c f unction ............................................................................................................................... ......................................... 12 6.4 gpio f unction ............................................................................................................................... ..................................... 12 6.5 w atchdog t imer f unction ............................................................................................................................... ................. 13 6.6 mcu f unction ............................................................................................................................... ...................................... 13 7 register description (i2c address = 0x9c)...................................................................................... .................... 15 7.1 d ata m emory s tructure and s pecial f unction r egister (sfr) s tructure .............................................................. 15 7.2 r eserved ? i ndex 0000 h ~0007 h ............................................................................................................................... .......... 16 7.3 r eserved ? i ndex 0008 h ............................................................................................................................... ....................... 16 7.4 r eserved ? i ndex 0009 h ............................................................................................................................... ....................... 16 7.5 r eserved ? i ndex 000a h ............................................................................................................................... ...................... 16 7.6 r eserved ? i ndex 000b h ............................................................................................................................... ...................... 17 7.7 r eserved ? i ndex 000c h ............................................................................................................................... ...................... 17 7.8 r eserved ? i ndex 000d h ............................................................................................................................... ...................... 17 7.9 cir ? cir fifo r egister ? i ndex 0010 h ............................................................................................................................ 17 7.10 cir ? i nterrupt e nable r egister ? i ndex 0011 h ......................................................................................................... 17 7.11 cir ? i nterrupt s tatus r egister ? i ndex 0012 h .......................................................................................................... 17 7.12 cir ? b aud r at e l ow b yte r egister ? i ndex 0013 h ................................................................................................... 17 7.13 cir ? b aud r at e h igh b yte r egister ? i ndex 0014 h .................................................................................................. 18
finte k feature integration technology inc. v0.20p 4 F16267 7.14 cir ? w av e f o r m l ogic 1 d ata r egister ? i ndex 0015 h .............................................................................................. 18 7.15 cir ? w av e f o r m l ogic 0 d ata r egister ? i ndex 0016 h .............................................................................................. 18 7.16 cir ? w av e f o r m l ogic 1 c ount r egister ? i ndex 0017 h ............................................................................................ 18 7.17 cir ? w av e f o r m l ogic 0 c ount r egister ? i ndex 0018 h ............................................................................................ 18 7.18 cir ? r x p rotocol r egister ? i ndex 0019 h ................................................................................................................. 18 7.19 gpio ? gpio c ontrol r egister ? i ndex 0020 h ............................................................................................................ 18 7.20 gpio ? gpio cap r egister ? i ndex 0021 h .................................................................................................................... 19 7.21 gpio ? gpio m ulti - function r egister ? i ndex 0022 h ............................................................................................... 19 7.22 gpio ? gpio d ata o utput r egister ? i ndex 0023 h ..................................................................................................... 19 7.23 gpio ? gpio i nput i nterrupt r egister ? i ndex 0024 h ............................................................................................... 19 7.24 gpio ? gpio s tatus r egister ? i ndex 0025 h ............................................................................................................... 19 7.25 gpio ? gpio l evel r egister ? i ndex 002f h ................................................................................................................. 19 7.26 i2c m aster ? i2c i nterrupt e nable r egister ? i ndex 0030 h .................................................................................... 19 7.27 i2c m aster ? i2c s tatus r egister ? i ndex 0031 h ........................................................................................................ 20 7.28 i2c m aster ? i2c d evice r egister ? i ndex 0032 h ....................................................................................................... 20 7.29 i2c m aster ? i2c r ead r egister ? i ndex 0033 h .......................................................................................................... 20 7.30 i2c m aster ? i2c i ndex id r egister ? i ndex 0034 h .................................................................................................... 20 7.31 i2c m aster ? i2c a ddress ? i ndex 0035 h ..................................................................................................................... 20 7.32 rtc ? s econd r egister ? i ndex 0080 h .......................................................................................................................... 20 7.33 rtc ? m inute r egister ? i ndex 0081 h .......................................................................................................................... 21 7.34 rtc ? h our r egister ? i ndex 0082 h .............................................................................................................................. 2 1 7.35 rtc ? d ay of w eek r egister ? i ndex 0083 h ................................................................................................................. 21 7.36 rtc ? d ate of m onth r egister ? i ndex 0084 h ............................................................................................................ 21 7.37 rtc ? m onth r egister ? i ndex 0085 h ........................................................................................................................... 21 7.38 rtc ? y ear r egister ? i ndex 0086 h .............................................................................................................................. 2 1 7.39 a larm ? s econd a larm r egister ? i ndex 0087 h ......................................................................................................... 22 7.40 a larm ? m inute a larm r egister ? i ndex 0088 h ......................................................................................................... 22 7.41 a larm ? h our a larm r egister ? i ndex 0089 h ............................................................................................................ 22 7.42 a larm ? d at e o f m onth a larm r egister ? i ndex 008a h .......................................................................................... 22 7.43 a larm ? m onth a larm r egister ? i ndex 008b h ......................................................................................................... 22 7.44 c ontrol r egister ? c ontrol r egister 1 ? i ndex 008c h ............................................................................................. 23 7.45 c ontrol r egister ? c ontrol r egister 1 ? i ndex 008d h ............................................................................................ 23 7.46 c ontrol r egister ? s tatus r egister ? i ndex 008e h ................................................................................................... 24 7.47 r eserved ? i ndex 008f h ............................................................................................................................... ................... 25 7.48 ram d ata r egister ?i ndex 0090 h ~00cf h (t otal 64 b ytes ) ..................................................................................... 25 7.49 w atchdog t imer e nable r egister ? i ndex 00fa h ...................................................................................................... 25
finte k feature integration technology inc. v0.20p 5 F16267 7.50 w atchdog t imer h igh n ibble r egister ? i ndex 00fb h .............................................................................................. 25 7.51 w atchdog t imer m iddle b yte r egister ? i ndex 00fc h ............................................................................................ 25 7.52 w atchdog t imer l ow b yte r egister ? i ndex 00fd h ................................................................................................. 25 8 ordering information ........................................................................................................... ....................................... 26 9 package dimensions (16-ssop) ................................................................................................... .................................. 26 10 application circuit ............................................................................................................ ............................................ 28
finte k feature integration technology inc. v0.20p 6 F16267 1 general description the F16267 is an 80c31 instruction compatible microc ontroller for general purpose system management. with external i2c serial eeprom(2k bytes), the F16267 provides the best extendable flexibility by different customized features and memory size, loading program through two wires i2c serial port will be easily to implement. furthermore, the F16267 supports one i2c slave serial ports to connect system chipset. the F16267 also supports 8 suits general purpose input / output pins and a low current consumption rtc. these functions of F16267 are implemented for different kind s of applications. major application fields are small home appliances or computer peripheral applications. t he F16267 is in ssop-16 package and powered by 3.3vcc. 2 feature ? compatible with 80c31 instructions ? supports cir for receive ? 2k bytes ram for loading the program from external eeprom ? 64 bytes ram of uc ? supports rtc with 64 bytes sram by 32.768khz ? supports 8 suits general purpose input / output ? hardware i2c slave functions ? used extend i2c eeprom storage code ? supports firmware power down /idle mode ? powered by 3.3vcc and packaged in ssop-16
finte k feature integration technology inc. v0.20p 7 F16267 3 pin configuration figure1. F16267 pin configuration
finte k feature integration technology inc. v0.20p 8 F16267 4 pin description 4.1. power pin pin no. pin name type description 5 vbat power source of rtc supplied from 3.3v battery 8 vss ground 16 vcc p power supply input 3.3v 4.2. gpio pin pin no. pin name type pwr description 4 gpio5 i/o 12st5v vdd general purpose input/output bit 5 11 gpio0 i/o 12st5v vdd general purpose input/output bit 0 12 gpio1 i/o 12st5v vdd general purpose input/output bit 1 13 gpio2 i/o 12st5v vdd general purpose input/output bit 2 14 gpio3 i/o 12st5v vdd general purpose input/output bit 3 15 gpio4 i/o 12st5v vdd general purpose input/output bit 4 4.3. rtc pin pin no. pin name type pwr description 6 xtal_32k_in ain vbat 32.768khz clock input 7 xtal_32k_in ain vbat 32.768khz clock output p - power pins in st5v - ttl level input pin with schmitt trigger i/od 12st5v - ttl level bi-directional pin with schmitt trigger, open-drain output with 12 ma sink capability, 5v tolerance i/o 12st5v - output pin with 12ma sink/driving capability.5v tolerance ain - input pin (analog). aout - output pin (analog).
finte k feature integration technology inc. v0.20p 9 F16267 4.4. i2c interface pin pin no. pin name type pwr description 2 i2cs_scl/gpio7 i/od 12st5v vdd i2c serial clock for slave function/ general purpose input output bit 7 3 i2cs_sda/gpio6 i/od 12st5v vdd i2c serial data for slave function/ general purpose input output bit 6 9 i2cm_sda i/od 12st5v vdd i2c serial data for load external rom function or other i2c salve device 10 i2cm_scl i/od 12st5v vdd i2c serial clock for load external rom function or other i2c salve device 4.5. ir pin pin no. pin name type pwr description 1 rx_in in st5v vdd ir receiver input
finte k feature integration technology inc. v0.20p 10 F16267 5 electrical characteristic 5.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 5.5 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to +70 c storage temperature -55 to 150 c note: exposure to conditions beyond those listed under abso lute maximum ratings may adversely affect the life and reliability of the device 5.2 dc characteristics (ta = 0 c to 70 c, vcc = 3.3v 10%, vss = 0v) parameter sym. min. typ. max. unit conditions operating voltage vdd 3.0 3.3 3.6 v battery voltage vbat 2.4 3.3 3.6 v operating current icc 35 ma vcc=3.3v vbat=3.3v idle state current isty 5 ua vcc=3.3v vbat=3.3v battery current ibat 4 ua vcc=3.3v vbat=3.3v i/od 12st5v - ttl level and schmitt trigger bi-directional pin with 12 ma source-sink capability 5v tolerance input low voltage vil 0.8 v input high voltage vih 2.0 v hysteresis 0.5 v output low current iol +12 ma vol = 0.4v input high leakage ilih -1 +1 a input low leakage ilil -1 +1 a i/o 12 ? output pin with12ma sour ce-sink capability ,5v tolerance input low voltage vil 0.8 v vdd = 3.3 v input high voltage vih 2.0 v vdd = 3.3 v hysteresis 0.5 v output high current ioh 12 ma voh = 2.0 v input high leakage ilih -1 +1 a input low leakage ilil -1 +1 a in ts_5v ? ttl level input pin and schmitt trigger, 5v tolerance input low voltage vil 0.8 v input high voltage vih 2.0 v hysteresis 0.5 v input high leakage ilih +1 a
finte k feature integration technology inc. v0.20p 11 F16267 input low leakage ilil -1 a 5.3 ac characteristics valid data scl sda in sda out t hd;sta t scl t hd;dat t su;sto t su;dat serial bus timing diagram t r t r t del;dat figure 2 smbus timing diagram serial bus timing parameter symbol min max unit scl clock period t - scl 3 us start condition hold time t hd;sda 50 ns stop condition setup-up time t su;sto 50 ns data to scl setup time t su;dat 50 ns data to scl hold time t hd;dat 5 ns data out to scl delay time t del:data 200 ns scl and sda rise time t r 200 ns scl and sda fall time t f 200 ns
finte k feature integration technology inc. v0.20p 12 F16267 6 functional description 6.1 cir function the cir is used in consumer remo te control equipment. it is progra mmable amplitude shift keyed (ask) serial communication protocol. by adjusting frequency, baud rate divisors, and sensitivit y ranges, the cir register are able to support the popular protocols such as it t, nec, nokia, sharp, sony and philips rc5./rc6 software driver programming can support new protocol . the cir builds 8 bytes fifo for data reception. 6.2 rtc function the F16267 provides a real-time-clock with 64 bytes of ram. the rtc provides a time-of-day clock in two data formats (binary or bcd) and two hour formats (24 hr or am/pm). the clock/calendar provides seconds, minutes, hours, day, date, month, year, and century info rmation. it also provides a special time update and corrections for leap years. it has one alarm and three programmable interrupts. the F16267 is designed with either a crystal oscillator or external clock. the F16267 incorporates a built-in crystal oscillator. to make the oscillator work, a crystal must be connected across xtal_32k_in pin and xtal_32k_out pin. in addition, an external clock should be connected to xtal_32k_in pin and xtal_32k_out pin should be unconnected. recommend to be connected with 32.768khz input. 6.3 i2c function the F16267 provides two i2c serial ports for transmission. the pins, i2c_sda_m and i2c_sda_m, are connected to external serial eeprom for different custom ized requirement to transmit or receive i2c salve device data. the pins, i2c_sda_s and i2c_sda_s, are for i2c slave function. the i2c slave function support byte read, byte write, continuous read (256 bytes), and continuous write (256 bytes) mode and it defaults to address at 8?h9c and its address can be programmed by the register. the i2c slave function supports real-time read or write internal data of rtc/cir/gpio. 6.4 gpio function the F16267 provides 8 suits general purpose input/outpu t. this function provides drives or sinks and input detects capability. the gpio6 and gpio7 are the multi-f unction pins with i2c_sda_s and i2c_scl_s. they can be switched by the register.
finte k feature integration technology inc. v0.20p 13 F16267 6.5 watchdog timer function the F16267 contains a watchdog timer which will reset the ic when it counts down the set value in register 0x00fb ~ 0x00fd (20 bits) to zero. the watchdog timer is based on 12mhz clock. 6.6 mcu function the F16267 is an 8031 based micro processor for general purpose system management. the instruction set of the F16267 is fully compatible with the standard 8031, but not provides timer1/uart function and multiplication/division operation. the F16267 utilizes the external 32.768khz crys tal to oscillate 12mhz internally instead of the external 12mhz crystal. the rest of the functions are as below description. the F16267 separates the memory into two separate sections, the program memory and the data memory. the program memory is used to store th e instruction op-codes, while the data memory is used to store data or for memory mapped devices. 6.6.1 program memory the program memory on the F16267 can be up to 2kbyte s long. all instructions are fetched for execution from this memory area. the movc instruct ion can also access this memory region. 6.6.2 data memory the F16267 can access internal device function (rtc/c ir/gpo) of external data memory mapping. this memory region is accessed by the movx instructions. a nd internal device is mapping in data memory region. in addition, the F16267 has the 128 bytes of on-chip scratc hpad ram. this can be accessed either by direct addressing or by indire ct addressing. there are also some special f unction registers (sfrs), which can only be accessed by direct addressing. since the scratchpad ram is only 128 bytes. table 1 3 source interrupt information interrupt source vector address enable required settings interrupt type edge/level external interrupt 0 03h ie.0 tcon.0 timer 0 interrupt 0bh ie.1 tcon.5 external interrupt 1 13h ie.2 tcon.2
finte k feature integration technology inc. v0.20p 14 F16267 table 2 2 source interrupt information interrupt source vector address function external interrupt 0 03h cir external interrupt 1 13h rtc/i2c master/gpio 6.6.3 power saving mode normal state: all internal devices are working, and the internal clock is on idle mode: when set sfr index 8?h87 bit 0=1, the F16267 goes into id le mode, and the clock will stop. if the internal devices like gpio, rtc, and cir are asserted interrupt, t he micro processor will resume the normal mode. power down mode: when set sfr index 8?h87 bit 1=1, the F16267 goes into power down mode, and the clock will stop. if the micro processor wants to be resumed the normal mode, power of f or software reset (register 16?h0005 bit 0) is necessary.
finte k feature integration technology inc. v0.20p 15 F16267 7 register description (i2c address = 0x9c) 7.1 data memory structure and special function register (sfr) structure 00ffh direct addressing (sfr) 0080h 007fh direct/indirect addressing 0000h figure 3 data memory structure
finte k feature integration technology inc. v0.20p 16 F16267 table 3 F16267 sfr memory allocation sfr address wdt clb clb7 clb6 clb5 clb4 clb3 clb2 clb1 clb0 fdh wdt mlb mlb7 mlb6 mlb5 mlb4 mlb3 mlb2 mlb1 mlb0 fch wdthlb hlb7 hlb6 hlb5 hlb4 hlb3 hlb2 hlb1 hlb0 fbh wdt en en status fah acc acc7 acc6 acc5 acc4 acc3 acc2 acc1 acc0 e0h psw cy ac f0 rs1 rs0 ov p d0h ip pt0 px0 b8h p3 p37 p36 p35 p34 p33 p32 p31 p30 b0h ie ea et0 ex0 a8h p2 p27 p26 p25 p24 p23 p22 p21 p20 a0h p1 p17 p16 p15 p14 p13 p12 p11 p10 90h th0 8bh tl0 8ah tmod gate c/t m1 m0 gate c/t m1 m0 89h tcon tf0 tr0 ie1 it1 ie0 it0 88h pcon smod gf1 gf0 pd idl 87h dph 83h dpl 82h sp 81h p0 p07 p06 p05 p04 p03 p02 p01 p00 80h 7.2 reserved ? index 0000h~0007h bit name r/w default description 7-0 reserved - 0 reserved 7.3 reserved ? index 0008h bit name r/w default description 7-0 reserved r - reserved 7.4 reserved ? index 0009h bit name r/w default description 7-0 reserved r - reserved 7.5 reserved ? index 000ah bit name r/w default description
finte k feature integration technology inc. v0.20p 17 F16267 7-0 reserved r 34h reserved 7.6 reserved ? index 000bh bit name r/w default description 7-0 reserved r 19h reserved 7.7 reserved ? index 000ch bit name r/w default description 7-0 reserved r 20h reserved 7.8 reserved ? index 000dh bit name r/w default description 7-0 reserved r 07h reserved 7.9 cir ? cir fifo register ? index 0010h bit name r/w default description 7-0 cir_fifo r 00h receiver buffer register is read only. when the cir pulse train has been detected and passed by the internal signal filter, the data sampled and shifted into shifter register will be written into receiver buffer register 7.10 cir ? interrupt enable register ? index 0011h bit name r/w default description 7 interrupt_en r/w 0 write 1 to enable cir interrupt. 6-0 reserved - 0 reserved 7.11 cir ? interrupt status register ? index 0012h bit name r/w default description 7-4 fifo_cnt r 0 this nibble indicates that how many byte rx data will be read. 3 fifo_rst r/w 0 write 1 to reset cir fifo 2 reserved r/w 0 reserved 1 data_lost r 0 this bit indicates fifo data lost, and write 1 to clear 0 ready r 0 this bit indicates rx data ready, and write 1 to clear 7.12 cir ? baud rate low byte register ? index 0013h bit name r/w default description 7-0 baud_lo r/w a5h the registers of bll are baud rate divisor latch.
finte k feature integration technology inc. v0.20p 18 F16267 7.13 cir ? baud rate high byte register ? index 0014h bit name r/w default description 7-0 baud_hi r/w 01h the registers of bhl are baud rate divisor latch. 7.14 cir ? waveform logic 1 data register ? index 0015h bit name r/w default description 7-0 waveh r/w 80h the registers of waveh indicate rx logic 1 waveform 7.15 cir ? waveform logic 0 data register ? index 0016h bit name r/w default description 7-0 wavel r/w 02h the registers of wavel indicate rx logic 0 count number 7.16 cir ? waveform logic 1 count register ? index 0017h bit name r/w default description 7-0 waveh_count r/w 80h the registers of waveh_count indicate rx logic 1 count number 7.17 cir ? waveform logic 0 count register ? index 0018h bit name r/w default description 7-0 wavel_count r/w 02h the registers of wavel_count indicate rx logic 0 count number 7.18 cir ? rx protocol register ? index 0019h bit name r/w default description 7 low_frequency r/w 1 write 1 to indicate rx carry frequency from 20k to 100k, and write 0 to indicate rx carry frequency from 400k to 500k. 6-5 reserved - 00 reserved 4 rxinv r/w 1 write 1 to indicate invert rx i nput, or to indicate by pass rx. 3 bypass r/w 1 write 1 to indicate rx input is demo dulation , or to indicate rx is un- demodulation 2-0 protocol r/w 001 000 : itt 001 : nec 010 : nokia 011 : sharp 100 : sony 101 : philips rc5 7.19 gpio ? gpio control register ? index 0020h bit name r/w default description
finte k feature integration technology inc. v0.20p 19 F16267 7-0 gpio_cntl r/w 00h every bit indicates the corresponding pad of gpio capability 0 : open drain, 1: drive/sink capability 7.20 gpio ? gpio cap register ? index 0021h bit name r/w default description 7-0 gpo_cap r/w 00h every bit indicates the corresponding pad of gpio direction 0 : input ,1: output 7.21 gpio ? gpio multi-function register ? index 0022h bit name r/w default description 7 int_global_en r/w 0 set to 1 to enable gpio global interr upt enable ,or to disable interrupt. 6-1 reserved - - reserved 0 gpio/i2c r/w 00h 0 : i2c function 1 : gpio function 7.22 gpio ? gpio data output register ? index 0023h bit name r/w default description 7-0 gpio_pdout r/w ffh gpio data output for pad. 7.23 gpio ? gpio input interrupt register ? index 0024h bit name r/w default description 7-0 gpio_int_en r/w 00h every bit indicates the corresponding input pad of gpio interrupt enable. 0: disable, 1: enable 7.24 gpio ? gpio status register ? index 0025h bit name r/w default description 7-0 gpio_status r/w 00h every bit indicates the corresponding input pad of gpio status write 1 to clear. 7.25 gpio ? gpio level register ? index 002fh bit name r/w default description 7-0 gpio_level r/w 00h every bit indicates the corresponding input gpio pad level. 7.26 i2c master ? i2c interrupt enable register ? index 0030h bit name r/w default description 7 i2c_global_int_en r/w 0 this bit indicates global interrupt enable 6-2 reserved - - reserved 1 i2c_read_int_en r/w 0 this bit indicates i2c read finish interrupt enable
finte k feature integration technology inc. v0.20p 20 F16267 0 i2c_write_int_en r/w 0 this bit indicates i2c write finish interrupt enable. 7.27 i2c master ? i2c status register ? index 0031h bit name r/w default description 7 i2c_nak r/w 0 this bit indicates nak response from i2c device, and be written 1 to clear. 6-4 reserved - - reserved 3 read_start r/w 0 write 1 to start i2c read function and be cleared to 0 when i2c read function finish. 2 read_status r/w 0 this bit indicates i2c read finish status, and writes 1 to clear 1 write_start r/w 0 write 1 to start i2c write function and be cleared to 0 when i2c write function finish. 0 write_status r/w 0 this bit indicates i2c write finish status, and writes 1 to clear 7.28 i2c master ? i2c device register ? index 0032h bit name r/w default description 7-0 device_data r/w 00h write this byte to indicate i2c star t transmit this byte data to device. 7.29 i2c master ? i2c read register ? index 0033h bit name r/w default description 7-0 read_data r 00h this byte indicates receive data from i2c device. 7.30 i2c master ? i2c index id register ? index 0034h bit name r/w default description 7 reserved - - reserved 6-4 device_new_id 0 this nibble indicates slave address the a0a1a2 of protocol. 3-0 device_id r/w 0 this nibble indicates slave address the highest nibble of protocol. 7.31 i2c master ? i2c address ? index 0035h bit name r/w default description 7 i2c_address r 00h this byte indicates address of i2c protocol 7.32 rtc ? second register ? index 0080h bit name r/w default description 7 reserved - 0 reserved 6-0 second r/w 0 to write this bit, ?set? bit (cr8c[7]) must be set to 1.
finte k feature integration technology inc. v0.20p 21 F16267 7.33 rtc ? minute register ? index 0081h bit name r/w default description 7 reserved - 0 reserved 6-0 minute r/w 0 to write this min, ?set? bit (cr8c[7]) must be set to 1. 7.34 rtc ? hour register ? index 0082h bit name r/w default description 7 pm_flag r/w 0 this bit is used to indicate that hour is at am or pm. it only makes sense when ?m24? bit (cr8c[1]) is set to 0. to write this bit, ?set? bit (cr8c[7]) must be set to 1. 0: am, 1: pm 6 reserved - 0 reserved 6-0 hour r/w 12h to write this bit, ?set? bit (cr8c[7]) must be set to 1. 7.35 rtc ? day of week register ? index 0083h bit name r/w default description 7-3 reserved - 0 reserved 2-0 week r/w 1 to write this bit, ?set? bit (cr8c[7]) must be set to 1. 001: sunday 010: monday 011: tuesday 101: thursday 110: friday 111: saturday 7.36 rtc ? date of month register ? index 0084h bit name r/w default description 6-4 reserved - 0 reserved 5-0 date r/w 1 to write this bit, ?set? bit (cr8c[7]) must be set to 1. 7.37 rtc ? month register ? index 0085h bit name r/w default description 6-4 reserved - 0 reserved 5-0 month r/w 1 to write this bit, ?set? bit (cr8c[7]) must be set to 1. 7.38 rtc ? year register ? index 0086h bit name r/w default description 6-4 reserved - 0 reserved
finte k feature integration technology inc. v0.20p 22 F16267 5-0 year r/w 07h to write this bit, ?set? bit (cr8c[7]) must be set to 1. 7.39 alarm ? second alarm register ? index 0087h bit name r/w default description 7 sec_alarm_en r/w 0 seconds alarm enable. to enable second alarm function to compare sec_alarm data set in [6:0] with second, this bit must be set to 1. if this bit is not set to 1, it means th at second alarm is not concerned. 6-0 sec_alarm r/w 00h seconds alarm data. 7.40 alarm ? minute alarm register ? index 0088h bit name r/w default description 7 min_alarm_en r/w 0 minutes alarm enable. to enable minute alarm function to compare min_alarm data set in [6:0 ] with minute, this bit mu st be set to 1. if this bit is not set to 1, it means th at minute alarm is not concerned. 6-0 min_alarm r/w 00h minutes alarm data. 7.41 alarm ? hour alarm register ? index 0089h bit name r/w default description 7 hrs_alarm_en r/w 0 hour alarm enable. to enable hour alarm function to compare pm_alarm data set in bit 6 and hrs_alarm data set in [5:0] with pm/hrs_flag, this bit must be set to 1. if this bit is not set to 1, it means that hour alarm is not concerned. 6 pm_alarm r/w 0 pm flag alarm data 5-0 hrs_alarm r/w 00h hours alarm data 7.42 alarm ? date of month alarm register ? index 008ah bit name r/w default description 7 date_alarm_en r/w 0 date alarm enable. to enable date alarm function to compare date_alarm data set in [5:0], this bit mu st be set to 1. if this bit is not set to 1, it means that date alarm is not concerned. 6 reserved r 0 reserved 5-0 date_alarm r/w 00h date of month alarm data 7.43 alarm ? month alarm register ? index 008bh bit name r/w default description 7 mth_alarm_en r/w 0 month alarm enable. to enable month alarm function to compare mth_alarm data set in [4:0], this bit must be set to 1. if this bit is not set to 1, it means that mont h alarm is not concerned. 6-5 reserved r 0 reserved
finte k feature integration technology inc. v0.20p 23 F16267 4-0 mth_alarm r/w 00h month alarm data 7.44 control register? control register 1 ? index 008ch bit name r/w default description 7 set r/w 0 set calendar registers (set) this bit must be set to 1 to while writing calendar registers. when this bit is set, the calendar update process will be stop. 6 pie r/w 0 periodic interrupt enable (pie) the bit is set to 1 to enable the generation of interrupt by pf (cr8e[6]). 5 aie r/w 0 alarm interrupt enable (aie) this bit is set to 1 to enable the ge neration of interrupt by uf (cr8e[5]). 4 uie r/w 0 update-ended interrupt enable (uie) this bit is set to 1 to enable the ge neration of interrupt by uf (cr8e[4]) 3 reserved r 0 reserved 2 dm r/w 0 data mode (dm) 0: binary coded decimal mode (bcd mode) 1: binary mode 1 m24 r/w 0 24/12 hours mode (m24) 0: am/pm 12 hours mode 1: 24 hours mode 0 dse r/w 0 daylight saving enable (dse) 0: disable special updates 1: enable special updates: (a) the first sunday of april, the ti me increases from am 01:59:59 to am 03:00:00. (b) the last sunday of october, t he time decreases from am 01:59:59 to am 01:00:00 7.45 control register? control register 1 ? index 008dh bit name r/w default description 7 uip r 0 update cycle in progress (uip). uip is cleared in the end of an update cycle or when ?set? (cr8c[7]) is 1. 6-4 reserved r/w 010b reserved
finte k feature integration technology inc. v0.20p 24 F16267 3-0 pir r/w 0000b periodic interru pt rate (pir) 0000: none 0001: 16 khz 0010: 8 khz 0011: 4 khz 0100: 2 khz 0101: 1 khz 0110: 512 hz 0111: 256 hz 1000: 128 hz 1001: 64 hz 1010: 32 hz 1011: 16 hz 1100: 8 hz 1101: 4 hz 1110: 2 hz 1111: 1 hz 7.46 control register? status register ? index 008eh bit name r/w default description 7 rtc_int_n r 1 rtc interrupt request flag (rtc_int_n). the interrupt request flag is set to 0 if one of the following cases are true: pf*pie = ?1? af*aie = ?1? uf*uie = ?1? 6 pf r 0 periodic interrupt flag (pf) this bit is set to 1 when a rising edge is detected on the selected pir clock. pf is set to 1 regardless of t he state of pie bit. this bit is cleared after cr8e is read. 5 af r 0 alarm interrupt flag (af) this bit is set to 1 when the current time has reached the alarm time. af is set to 1 regardless of the state of aie bit. this bit is cleared after cr8e is read. 4 uf r 0 update-ended interrupt flag (uf) this bit is set to 1 after the end of each update cycle. uf is set to 1 regardless of the state of uie bit. this bit is cleared after cr8e is read. 3-0 reserved r 0 reserved
finte k feature integration technology inc. v0.20p 25 F16267 7.47 reserved ? index 008fh bit name r/w default description 7-0 reserved r 80 reserved 7.48 ram data register ?index 0090h~00cfh (total 64 bytes) 7.49 watchdog timer enable register ? index 00fah bit name r/w default description 7 watchdog_en r/w 0 set to 1 to enable watch dog timer and start count down. reserved r 0 4-0 watchdog_status r/w 0 set to 1, when watch dog timer count down to 0. write 1 to clear. 7.50 watchdog timer high nibble register ? index 00fbh bit name r/w default description 7-4 reserved - 0 reserved 3-0 time_high_nibble r/w 0 this register sets watch dog time[19:16] 7.51 watchdog timer middle byte register ? index 00fch bit name r/w default description 7-0 time_middle_byte r/w 0 this register sets watch dog time[15:8] 7.52 watchdog timer low byte register ? index 00fdh bit name r/w default description 7-0 time_low_byte r/w 0 this register sets watch dog time[7:0]
finte k feature integration technology inc. v0.20p 26 F16267 8 ordering information part number package type production flow F16267r 16-ssop (green package) commercial, 0 c to +70 c 9 package dimensions (16-ssop) figure 4. 16 pin ssop package diagram
finte k feature integration technology inc. v0.20p 27 F16267 please note that all datasheet and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037 www: http://www.fintek.com.tw
finte k feature integration technology inc. v0.20p 28 F16267 10 application circuit figure 5. F16267r application circuit

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